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19-1056; Rev 0; 11/07
DVI/HDMI 2:4 Low-Frequency Fan Out Switch
General Description
The MAX4814E high-definition multimedia interface (HDMI) switch provides routing for low-frequency signals. The MAX4814E operates from a single +5.0V 10% supply voltage and is ideal for connecting multiple HDMI sources to multiple loads. The MAX4814E is a bidirectional 2:4 HDMI switch. Each switch consists of five single-pole/single-throw (SPST) channels. Two channels have a low 3 (typ) on-resistance to route +5V and drain (ground return), and three channels to route data. The device features a mode input to control the device through an I2C interface or direct-control logic inputs. The MAX4814E is available in a 64-pin (10mm x 10mm) TQFP package and operates over the -40C to +85C extended temperature range. +5V/Drain Switched HPD (Hot-Plug Detect) Switching DDC (Display Data Channel) Switching Direct Entry or I2C Control Low 1A Quiescent Current 6kV Human Body Model (HBM) ESD Protection on Switch I/Os Companion IC to the MAX3845 Provides I2C Control for the MAX3845 Compact 64-Pin, 10mm x 10mm TQFP Package Optimized Layout to Support 4:4 or 2:8 Configuration with Two Devices
Features
MAX4814E
Applications
Commercial/Industrial HDMI/DVI Switch Boxes High-End Consumer Switchers AV Receivers with Switching
PART
Ordering Information
TEMP RANGE PINPACKAGE 64 TQFP-EP* PKG CODE C64E-10
MAX4814EECB+ -40C to +85C
+Denotes a lead-free package. *EP = Exposed paddle.
Pin Configuration appears at end of data sheet.
Typical I2C Operating Circuit
4.5V TO 5.5V
0.1F
DVI/HDMI 1
5
MODE
A
VDD
SW0 SW1
5 5 5 5
DVI/HDMI 1 OR DVI/HDMI 2 DVI/HDMI 1 OR DVI/HDMI 2 DVI/HDMI 1 OR DVI/HDMI 2 DVI/HDMI 1 OR DVI/HDMI 2
DVI/HDMI 2
5
B
SW2 SW3
VDD
MAX4814E
CONTROLLER SCL SDA
AD2 ADDRESS SELECTION* AD1 AD0 DO EFN 0.1F *SEE DEVICE ADDRESS SECTION. 4 MAX3845
GND
________________________________________________________________ Maxim Integrated Products
1
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch MAX4814E
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND. Note 1.) VDD, A_, B_, SW_, EFN..........................................-0.3V to +6.0V All Other Pins (except GND).........................-0.3V to VDD + 0.3V Continuous Current, A_, B_ ..............................................60mA Continuous Current, VDD or GND...................................100mA Continuous Power Dissipation (TA = +70C) 64-Pin TQFP (derate 31.3mW/C above +70C)........2508mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering) .........................................+300C
Note 1: EFN must be either connected to VDD or left unconnected. EFN must not be connected to ground.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V 10%, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, VDD = +5V. Note 2.)
PARAMETER Power-Supply Voltage Power-Supply Current EFN Leakage Current LOGIC INPUTS (DA_, DB_, MODE, AD_) Input Low Voltage DA_, DB_ Input High Voltage DA_, DB_ Input-Voltage Hysteresis DA_, DB_ Input Low Voltage AD_ Input High Voltage AD_ Input-Voltage Hysteresis AD_ Input Low Voltage MODE Input High Voltage MODE Input-Voltage Hysteresis MODE Input Leakage Current DA_, DB_ Input Leakage Current AD_ Input Leakage Current MODE LOGIC OUTPUTS DO_ Output-Voltage Low Output-Voltage High Output Leakage Current Output Rise Time Output Short-Circuit Current VOL VOH IL tR ISC MODE = VDD, ISINK = 30A MODE = VDD, ISOURCE = 26A MODE = VDD, output at high impedance, VIN = 1.5V VOUT from 0.8V to 2.2V, CLOAD = 10pF ISOURCE ISINK 600 -1 +3 2 1 0.5 V V A ns mA VIL VIH VHYST VIL VIH VHYST VIL VIH VHYST IL IL IL MODE = 0V MODE = VDD 2 150 1 1 1 MODE = 0V MODE = 0V MODE = 0V MODE = VDD MODE = VDD MODE = VDD 2 150 0.8 2 150 0.8 0.8 V V mV V V mV V V mV A A A SYMBOL VDD IDD IL EFN = unconnected; all inputs = 0; all outputs high or low, no loads VEFN = VDD - 0.2V -2 CONDITIONS MIN 4.5 TYP 5 MAX 5.5 10 +2 UNIT V A A
2
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 10%, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, VDD = +5V. Note 2.)
PARAMETER ANALOG SWITCHES On-Resistance Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] On-Resistance-Flatness Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] On-Channel -3dB Bandwidth Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] Off-Isolation Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] Crosstalk Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] On-Capacitance Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] Off-Capacitance Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] Charge Injection On-Resistance +5V/Drain: A[0], A[4], B[0], B[4] Switch Leakage Current Input Low Voltage Input High Voltage Input-Voltage Hysteresis Input Leakage Current Output-Voltage Low SDA Serial Clock Frequency Hold Time (Repeated) START Condition (after this period the first clock pulse is generated) Low Period of the SCL Clock RON VIN = 2.5V, IIN = 10mA 12 SYMBOL CONDITIONS MIN TYP MAX UNIT
MAX4814E
RFLAT
VIN = 0.8V, 2.5V, 3.7V
2.5
BW
RS = RL = 50, CL = 35pF, Figure 1
190
MHz
VISO VCT CON COFF Q RON
RS = RL = 50, f = 1MHz, Figure 1 RS = RL = 50, f = 1MHz, Figure 1 VDD = 4.5V, f = 1MHz, Figure 2 VDD = 4.5V, f = 1MHz, Figure 2 VGEN = 1.5V, RGEN = 0, CL = 100pF, Figure 3 VDD = 4.5V, VIN = 0V or VDD
65 75 37 15 13 3 10 0.8 2.4 450 1
dB dB pF pF pC A V V mV A V kHz s s 0.4
IL 2C SPECIFICATIONS (SDA, SCL, MODE = VDD) I VIL VIH VHYST IL VOL fSCL tHD,STA tLOW ISINK = 3mA VDD = 4.5V fSCL = 100kHz fSCL = 100kHz 100 4 4.7 400
TIMING CHARACTERISTICS (Figure 4), MODE = VDD
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch MAX4814E
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 10%, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, VDD = +5V. Note 2.)
PARAMETER High Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SW_, A_, B_ All Other I/Os SYMBOL tHIGH tSU,STA tHD,DAT tSU,DAT CONDITIONS fSCL = 100kHz fSCL = 100kHz fSCL = 100kHz fSCL = 100kHz Referenced to GND MIN 4 4.7 25 250 6 2 TYP MAX UNIT s s s ns
ESD PROTECTION (HUMAN BODY MODEL) ESD kV
Note 2: Limits at TA = -40C are guaranteed by design.
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch MAX4814E
+5V 0.1F OFF-ISOLATION = 20log NETWORK ANALYZER VDD A_ B_ 50 GND VIN 50 50 ON-LOSS = 20log
VOUT VIN VOUT VIN
MAX4814E
SW_ VOUT
MEAS
REF
V CROSSTALK = 20log OUT VIN
50
50
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN SW_ AND "OFF" A_ OR B_ TERMINAL ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN SW_ AND "ON" A_ OR B_TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO ALL OTHER CHANNELS. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 1. On-Loss, Off-Isolation, and Crosstalk
0.1F
+5V
VDD SW_
MAX4814E
DB_ DA_ OR SDA SCL VIL OR VIH
CAPACITANCE METER f = 1MHz
A_ OR B_ GND
Figure 2. Channel Off-/On-Capacitance
+5V
0.1F VOUT DB_ DA_ OR SDA SCL DB_ DA_ OR SDA SCL
MAX4814E
VDD RGEN A_ OR B_ GND DB_ SDA OR SCL DA_ VINL TO VINH SW_ CL VOUT
VOUT
OFF
ON
OFF
V GEN
OFF
ON Q = (V OUT )(C L )
OFF
IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 3. Charge Injection
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch MAX4814E
Typical Operating Characteristics
(VDD = +5V, TA = +25C, unless otherwise noted.)
ON-RESISTANCE vs. VA OR VB
MAX4814E toc01
ON-RESISTANCE vs. VA OR VB
16 14 ON-RESISTANCE () 12 10 8 6 4 2 1 - - - - +5V/DRAIN 0 1 2 3 4 5 TA = +85C TA = -40C TA = +25C TA = -40C TA = +85C TA = +25C
MAX4814E toc02
LEAKAGE CURRENT vs. TEMPERATURE
+5V/DRAIN OFF-LEAKAGE 10,000 LEAKAGE CURRENT (pA) 1000 100 10 STD. SWITCH OFF-LEAKAGE +5V/DRAIN ON-LEAKAGE
MAX4814E toc03
18 16 14 ON-RESISTANCE () 12 10 8 6 4 2 0 0 - - - - +5V/DRAIN 1 2 3 VA OR VB (V) VDD = 5.5V 4 5 6 VDD = 4.5V VDD = 5.0V VDD = 5.0V VDD = 4.5V VDD = 5.5V
18
100,000
STD. SWITCH ON-LEAKAGE 0.1 -40 -15 10 35 60 85 TEMPERATURE (C)
0
VA OR VB (V)
SUPPLY CURRENT vs. TEMPERATURE
0.45 0.4 SUPPLY CURRENT (A) 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 VDD = 4.5V VDD = 5.0V VDD = 5.5V
MAX4814E toc04
FREQUENCY RESPONSE
MAX4814E toc05
0.5
20 0 FREQUENCY RESPONSE (dB) OFF-ISOLATION -20 -40 -60 -80 CROSS-TALK ON-LOSS
SWITCH I/O_ = 0V -40 -15 10 35 60 85
-100 0.1 1 10 FREQUENCY (MHz) 100 1000
TEMPERATURE (C)
6
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch
Pin Description
PIN 1, 16, 24, 25, 33, 48, 56, 57 2, 15, 34 3 4 5 6 7 8, 9, 17, 32, 40, 41, 49, 64 10 11 12 13 14 18 19 20 21 22 23 26 27 28 29 30 31, 50 35 36 37 38 39 42 43 44 NAME GND I.C. A[0] A[1] A[2] A[3] A[4] VDD B[0] B[1] B[2] B[3] B[4] MODE SDA SCL AD0 AD1 AD2 SW3[4] SW3[3] SW3[2] SW3[1] SW3[0] EFN SW2[4] SW2[3] SW2[2] SW2[1] SW2[0] SW1[4] SW1[3] SW1[2] FUNCTION Ground. Must connect all GND pins together. Internally Connected. Leave I.C. unconnected Switch A I/O 0. A[0] has a 3 (typ) resistance to switch 5V or drain. Switch A I/O 1. A[1] has a 12 (typ) resistance to switch data. Switch A I/O 2. A[2] has a 12 (typ) resistance to switch data. Switch A I/O 3. A[3] has a 12 (typ) resistance to switch data. Switch A I/O 4. A[4] has a 3 (typ) resistance to switch 5V or drain. Positive-Supply Voltage Input. Connect VDD to a +5V supply voltage. Bypass VDD to GND with a 0.1F capacitor. Must connect all VDD pins together. Switch B I/O 0. B[0] has a 3 (typ) resistance to switch 5V or drain. Switch B I/O 1. B[1] has a 12 (typ) resistance to switch data. Switch B I/O 2. B[2] has a 12 (typ) resistance to switch data. Switch B I/O 3. B[3] has a 12 (typ) resistance to switch data. Switch B I/O 4. B[4] has a 3 (typ) resistance to switch 5V or drain. MODE Selection Input. Connect MODE to VDD (MODE = 1) to select I2C control mode. Connect MODE to GND (MODE = 0) to select direct-control mode. I2C-Compatible Serial Data I/O I2C-Compatible Serial Clock Input Programmable I2C Address Bit. AD[0] sets the I2C address of the device. Userselectable device address bit, LSB, LSB+1, MSB (see Figure 5). Programmable I2C Address Bit. AD[1] sets the I2C address of the device. Userselectable device address bit, LSB, LSB+1, MSB (see Figure 5). Programmable I2C Address Bit. AD[2] sets the I2C address of the device. Userselectable device address bit, LSB, LSB+1, MSB (see Figure 5). Switch 3 I/O 4 Switch 3 I/O 3 Switch 3 I/O 2 Switch 3 I/O 1 Switch 3 I/O 0 ESD Protection. Connect EFN with an external 0.1F capacitor to GND for 15kV ESD HBM protection. The capacitor from EFN to GND provides an additional discharge path for the ESD energy. Switch 2 I/O 4 Switch 2 I/O 3 Switch 2 I/O 2 Switch 2 I/O 1 Switch 2 I/O 0 Switch 1 I/O 4 Switch 1 I/O 3 Switch 1 I/O 2
MAX4814E
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch MAX4814E
Pin Description (continued)
PIN 45 46 47 51 52 53 54 55 58 NAME SW1[1] SW1[0] N.C. SW0[4] SW0[3] SW0[2] SW0[1] SW0[0] DA0/DO0 Switch 1 I/O 1 Switch 1 I/O 0 No Connection. Not internally connected. Switch 0 I/O 4 Switch 0 I/O 3 Switch 0 I/O 2 Switch 0 I/O 1 Switch 0 I/O 0 Direct-Control Bit I/O. In mode 0, DA0/DO0 is set as an input, DA0, to control switch connections. In mode 1, DA0/DO0 is set as an output, DO0. The output bits are used to drive the MAX3845. Direct-Control Bit I/O. In mode 0, DA1/DO1 is set as an input, DA1, to control switch connections. In mode 1, DA1/DO1 is set as an output, DO1. The output bits are used to drive the MAX3845. Direct-Control Bit I/O. In mode 0 DA2/DO2 is set as an input, DA2, to control switch connections. In mode 1, DA1/DO1 is set as an output, DO2. The output bits are used to drive the MAX3845. Direct-Control Bit I/O. In mode 0 DB0/DO3 is set as an input, DB0, to control switch connections. In mode 1, DB0/DO3 is set as an output, DO3. The output bits are used to drive the MAX3845. Direct-Control Bit I/O. In mode 0, DB1 is set as an input. In mode 1, DB1 is high impedance. Direct-Control Bit I/O. In mode 0, DB1 is set as an input. In mode 1, DB1 is high impedance. Exposed Pad. Connect exposed pad to ground. For enhanced thermal dissipation, connect EP to a copper area as large as possible. Do not use EP as a sole ground connection. FUNCTION
59
DA1/DO1
60
DA2/DO2
61
DB0/DO3
62 63
DB1 DB2
EP
EP
Detailed Description
The MAX4814E provides routing for low-frequency DVI/HDMI signals. The MAX4814E is a bidirectional 2:4 DVI/HDMI switch. Each switch consists of five singlepole/single-throw (SPST) channels. The channels have a low 3 (typ) on-resistance to route +5V and drain, and three channels to route data. Channels A0, A4, B0, B4, SW_0, and SW_4 have a 3 (typ) on-resistance to route +5V and drain, and the remaining channels A1-A3, B1-B3, SL0_3, and SW_1 have a 12 (typ) on-resistance to route data. The device features a mode input to control the device using direct-control logic inputs or an I2C interface. Connect MODE to GND to control the device using the direct-control bits. Connect MODE to VDD to control the device using I2C. In I2C mode, the MAX4814E controls the MAX3845 (see Figure 5).
Analog Signal Levels
Signal inputs over the full voltage range (0V to VDD) are passed through the switch with minimal change in onresistance (see the Typical Operating Characteristics). The switches are bidirectional. Therefore, switch A_, switch B_, and switch SW_ can be either inputs or outputs.
Switch Control
The MAX4814E features a mode input to control the device through either an I2C interface or through directcontrol logic inputs. Connect MODE to GND (mode 0) to control the device using the direct-control inputs DA_ and DB_ (see Table 1 and Figure 6). Connect MODE to VDD (mode 1) to control the device using the I2C interface.
Direct Control Method (Mode 0) In mode 0, DA0/DO0 becomes input DA0, DA1/DO1
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch
Functional Diagram
VDD A_ 5 A0 A1 A2 A3 B_ 5 B0 B1 B2 B3 B_ DECODER 6 MUX 6 6 A_ 5 5 5 5 SW0_ SW1_ SW2_ SW3_
MAX4814E
MAX4814E
DO[3:0] 4 6 4 4 I2C SERIAL PORT AND REGISTERS HI-Z
4 DB0 DA_
I.C. N.C. EFN
EN
EN
EN
EN
EN
GND
MODE
SDA
SCL
AD0
AD1
AD2
DB_ DA_
becomes input DA1, DA2/DO2 becomes input DA2, and DB0/DO3 becomes input DB0. Inputs DB1 and DB2 are enabled. In mode 0, the direct-control inputs DA_ and DB_ are used to control the connection of the switches. DA2 is
used as the enable for switch A, and DB2 is used as the enable for switch B. Connecting DA2 to VDD enables switch A, and connecting DA2 to GND disables switch A. Connecting DB2 to VDD enables switch B, and connecting DB2 to GND disables switch B. Inputs DA0 and
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch MAX4814E
DA1 select the connections of switch A to switch SW_ and inputs DB0 and DB1. Select the connections of switch B to SW_. See Table 3a for the pin configuration and Table 3b for a complete summary. select the connections of switch B to switch SW_, as summarized in Table 6.
I2C Interface Method (Mode 1) In mode 1, the switch connections are controlled through the I2C interface. Inputs SDA and SCL program registers R0 and R1. Register R0, bits [7 to 2], select the connection of switch A and switch B to switch SW_ (see the I2C Registers and Bit Descriptions section). The bits of register R1 transfer data to the output DO_. The data on output DO_ is used to communicate with the MAX3845. In mode 1, DA0/DO0 becomes output DO0, DA1/DO1 becomes output DO1, DA2/DO2 becomes output DO2, and DB0/DO3 becomes output DO3. DB1 and DB2 are high impedance. See Table 3a for the pin configuration. See Table 4 for register R1 to DO_ output mapping. I2C Registers and Bit Descriptions
Two internal registers (RO and R1) program the MAX4814E. Table 2 lists both registers, their addresses, and power-up default states. Both registers are read/write registers. In register R0, bit BAEN is used as the enable for switch A, and bit BBEN is used as the enable for switch B. Writing 1 to bit BAEN enables switch A; and writing 0 to bit BAEN disables switch A. Writing 1 to bit BBEN enables switch B, and writing 0 to bit BBEN disables switch B. BASEL1 and BASEL0 select the connections of switch A to switch SW_, while BBSEL1 and BBSEL0
I2C Register R0 Two LSB Bits The two LSBs are hard coded as 00. Register R0 ignores any value written to the two LSBs; anytime register R0 is read the hard-coded values are returned. Bank A Enable (BAEN) and Bank B Enable (BBEN) Bits 1 = Enable 0 = Disable Bank A Select (BASEL1/BASEL0) and Bank B Select (BBSEL1/BBSEL0) Bits Bits BASEL1 and BASEL0 select the switch SW_ that switch A is connected to. Bits BBSEL1 and BBSEL0 select the switch SW_ that switch B is connected to (see Table 6).
Power-On Default States
When power is applied to the MAX4814E internal power-on reset (POR), circuitry sets registers R0 and R1 to their default states. Register R0 is set to all zeros, or 00h, and register R1 is set to 10101010, or AAh, as shown in Table 2. Having all zeros in register R0 disables both banks A and B; see Table 6 for register R0 to switch mapping. Setting register R1 to AAh forces the outputs at DO_ to be high impedance. Note: The output, DO_ is used to communicate with the MAX3845 when the MAX4814E is being used without its companion. The MAX3845 and the MAX4814E use the I2C interface (MODE = 1). All DO_ outputs need to be connected through a 10k resistor to GND.
Table 1. Mode Configuration
INPUT PIN MODE 0 1 OPERATION Puts the device in mode 0. The direct-control inputs DA_ and DB_ control the switches. Puts the device in mode 1. The switches are controlled by the I2C interface. DO_ becomes an active output. Inputs DB1 and DB2 are high impedance.
Table 2. I2C Register Map
BIT REGISTER R0 7 BBEN DO3 High Impedance 6 BBSE L1 DO3 Data 5 BBSEL0 DO2 High Impedance 4 BAEN DO2 Data 3 BASEL1 DO1 High Impedance 2 BASE L0 DO1 Data 1 X DO0 High Impedance 0 X DO0 Data ADDRESS 0x00 POWER-UP BINARY 0000 0000 1010 1010 HEX 00
R1
0x01
AA
X = Hardwired code, not programmable by user.
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch
Table 3a. Input/Output Configurations for DA_, DB_, and DO_
MODE 0 1 PIN CONFIGURATION DA0/DO0 DA0, Input DO0, Output DA1/DO1 DA1, Input DO1, Output DA2/DO2 DA2, Input DO2, Output DB0/DO3 DB0, Input DO3, Output DB1 DB1, Input High Impedance DB2 DB2, Input High Impedance
MAX4814E
Table 3b. Mode 0 Direct-Control Configurations
PIN CONNECTION DA2 0 1 Bank A switches are disabled Bank A switches are enabled. Switch A connections depend on the DA0 and DA1 inputs. OPERATION
PIN CONNECTION DB2 0 1 Bank B switches are disabled
OPERATION
Bank B switches are enabled. Switch B connections depend on the DB0 and DB1 inputs.
PIN CONNECTION DB1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DB0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
OPERATION Connect A to SW0 Connect A to SW1 Connect A to SW2 Connect A to SW3 Connect A to SW0 Connect A to SW1 Connect A to SW2 Connect A to SW3 Connect A to SW0 Connect A to SW1 Connect A to SW2 Connect A to SW3 Connect A to SW0 Connect A to SW1 Connect A to SW2 Connect A to SW3 B is high impedance Connect B to SW0 Connect B to SW0 Connect B to SW0 Connect B to SW1 B is high impedance Connect B to SW1 Connect B to SW1 Connect B to SW2 Connect B to SW2 B is high impedance Connect B to SW2 Connect B to SW3 Connect B to SW3 Connect B to SW3 B is high impedance
Note: When switch A and switch B are connected to the same SW_, switch A takes precedence and switch B is high impedance.
I2C Interface
The MAX4814E features an I 2 C interface using a repeated start. The MAX4814E I2C interface refers to the I2C bus specification (version 2.1, Jan 2000).
Device Address
The MAX4814E has selectable device addresses through external inputs. The slave address consists of four fixed bits (B7-B4, set to 0111) followed by three pinprogrammable bits (AD2-AD0), as shown on Table 7.
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch MAX4814E
Table 4. I2C Register R1 (0X01) to DO_ Mapping
PIN MODE 1 1 1 1 1 1 1 1 1 1 1 1 BIT 7 -- -- -- -- -- -- -- -- -- 0 0 1 BIT 6 -- -- -- -- -- -- -- -- -- 0 1 X BIT 5 -- -- -- -- -- -- 0 0 1 -- -- -- REGISTER R1 (0x01) BIT 4 -- -- -- -- -- -- 0 1 X -- -- -- BIT 3 -- -- -- 0 0 1 -- -- -- -- -- -- BIT 2 -- -- -- 0 1 X -- -- -- -- -- -- BIT 1 0 0 1 -- -- -- -- -- -- -- -- -- BIT 0 0 1 X -- -- -- -- -- -- -- -- -- OUTPUT PIN CONFIGURATION DO0 DO0 DO0 DO1 DO1 DO1 DO2 DO2 DO2 DO3 DO3 DO3 0 1 Hi-Z 0 1 Hi-Z 0 1 Hi-Z 0 1 Hi-Z
X = Don't care.
Table 5. I2C Register R0 (0x00)
REGISTER R0 (0x00) BIT 7 BBEN BIT 6 BBSEL1 BIT 5 BBSEL0 BIT 4 BAEN BIT 3 BASEL1 BIT 2 BASEL0 BIT 1 X BIT 0 X
X = hardwired, not programmed by user.
For example: If AD0, AD1, and AD2 are hardwired to ground, then the complete address is 0111000. The full address is defined as the seven most significant bits followed by the read/write bit. Set the read/write bit to 1 to configure the MAX4814E to read mode. Set the read/write bit to 0 to configure the MAX4814E to write mode. The address is the first byte of information sent to the MAX4814E after the START condition. .
damage. The ESD structures withstand high ESD in normal operation, and when the device is powered down. ESD protection can be tested in various ways. The ESD protection of switch A, switch B, and switch SW_ are characterized for 6kV (Human Body Model) using the MIL-STD-883.
ESD Test Conditions
ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results.
Applications Information
ESD Protection
As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. Switch A, switch B, and switch SW_ are further protected against static electricity. Maxim's engineers have developed state-of-the-art structures to protect these pins against ESD up to 6kV without
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Human Body Model
Figure 7 shows the Human Body Model, and Figure 8 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest that is then discharged into the test device through a 1.5k resistor.
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DVI/HDMI 2:4 Low-Frequency Fan Out Switch
Table 6. Switch Selection Truth Table
DA_, DB_ INPUTS/REGISTER R0 BITS DB2/ BBEN 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DB1/ BBSEL1 X X X X X 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 DB0/ BBSEL0 X X X X X 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 DA2/ BAEN 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 DA1/ DA0/ BASEL1 BASEL0 X 0 0 1 1 X 0 0 1 1 X 0 0 1 1 X 0 0 1 1 X 0 0 1 1 X 0 1 0 1 X 0 1 0 1 X 0 1 0 1 X 0 1 0 1 X 0 1 0 1 B TO SW3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 0 SWITCH A AND B TO SW_ CONNECTIONS B TO SW2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 0 1 -- -- -- -- -- B TO SW1 -- -- -- -- -- -- -- -- -- -- 1 1 0 1 1 -- -- -- -- -- -- -- -- -- -- B TO SW0 -- -- -- -- -- 1 0 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A TO SW3 -- -- -- -- 1 -- -- -- -- 1 -- -- -- -- 1 -- -- -- -- 1 -- -- -- -- 1 A TO SW2 -- -- -- 1 -- -- -- -- 1 -- -- -- -- 1 -- -- -- -- 1 -- -- -- -- 1 -- A TO SW1 -- -- 1 -- -- -- -- 1 -- -- -- -- 1 -- -- -- -- 1 -- -- -- -- 1 -- -- A TO SW0 -- 1 -- -- -- -- 1 -- -- -- -- 1 -- -- -- -- 1 -- -- -- -- 1 -- -- --
MAX4814E
-- = Denotes no connection. 1 = Denotes switch connection. 0 = Denotes switch B is high impedance. X = Don't care.
Table 7. MAX4814E Device Address
B7 0 B6 1 Fixed B5 1 B4 1 B3 AD2 B2 AD1 User Selected B1 AD0 B0 R/W --
Power-Supply Biasing and Sequencing
Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings, since stresses beyond the listed ratings can cause permanent damage to the device. Always
sequence VDD on first, followed by the switch inputs and the logic inputs. Bypass at least one VDD input to ground with a 0.1F capacitor as close as possible to the device. Use the smallest physical size possible for optimal performance.
13
______________________________________________________________________________________
DVI/HDMI 2:4 Low-Frequency Fan Out Switch MAX4814E
SDA tSU, DAT tLOW SCL tHD, STA tr START CONDITION tHIGH tf REPEATED START CONDITION tHD, DAT tSU, STA
Figure 4. 2-Wire Interface Timing Diagram
MODE = 1: I2C CONTROL 58 59
3-STATE CONTROL 96 65 61 30
MODE = 0: DIRECT CONTROL
MAX4814E
18 19 20 23 22 21
60 61
MAX3845
MAX4814E
18 21 22 23 61 62 63
VDD SDA SCL
I2C CONTROL
SETS 3 LSBs OF I2C ADDRESS. AS SHOWN ADDRESS = 0111 + LSB = 0111000. THERE ARE 8 POSSIBLE I2C ADDRESSES. BY HARDWIRING PINS 23, 22, AND 21 TO 1 OR 0 USER CAN CHANGE ADDRESS. SEE TABLE 4 FOR I2C REGISTERS.
MODE = 0
DA0 DA1 DA2 DB0 DB1 DB2
SEE TABLE 3b FOR CONTROL FUNCTIONS.
Figure 5. Mode 1: I2C Control
Figure 6. Mode 0: Direct Control
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1500 DISCHARGE RESISTANCE DEVICE UNDER TEST
IP 100% 90% AMPERES
Ir
PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
Cs 100pF
STORAGE CAPACITOR
36.8% 10% 0 0 tRL TIME tDL CURRENT WAVEFORM
Figure 7. Human Body ESD Test Model
Figure 8. Human Body Current Waveform
14
______________________________________________________________________________________
DVI/HDMI 2:4 Low-Frequency Fan Out Switch
Pin Configuration
TOP VIEW
SW1[0] SW1[1] SW1[2] SW1[3] SW1[4] SW2[0] SW2[1] SW2[2] SW2[3] SW2[4] GND GND N.C.
MAX4814E
VDD
VDD
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD 49
EFN 50 SW0[4] 51 SW0[3] 52 SW0[2] 53 SW0[1] 54 SW0[0] 55 GND 56 GND 57 DA0/DO0 58 DA1/DO1 59 DA2/DO2 60 DB0/DO3 61 DB1 62 DB2 63 *EP
I.C.
32 VDD 31 EFN 30 SW3[0] 29 SW3[1] 28 SW3[2] 27 SW3[3] 26 SW3[4] 25 GND
MAX4814E
24 GND 23 AD2 22 AD1 21 AD0 20 SCL 19 SDA 18 MODE 17 VDD
VDD 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A[0]
GND
A[1]
A[2]
A[3]
A[4]
I.C.
VDD
VDD
TQFP
*CONNECT EXPOSED PADDLE TO GND.
GND
B[0]
B[1]
B[2]
B[3]
B[4]
I.C.
It is also recommended to bypass more than one VDD input. A good strategy is to bypass one VDD input with a 0.1F capacitor and at least a second VDD input with a 1nF to 10nF capacitor (use a 0603 or smaller physical size ceramic capacitor).
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________
15
DVI/HDMI 2:4 Low-Frequency Fan Out Switch MAX4814E
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 64L, TQFP.EPS
PACKAGE OUTLINE, 64L TQFP, 10x10x1.0mm EP OPTION
21-0084
C
1
2
16
______________________________________________________________________________________
DVI/HDMI 2:4 Low-Frequency Fan Out Switch
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX4814E
PACKAGE OUTLINE, 64L TQFP, 10x10x1.0mm EP OPTION
21-0084
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
(c) 2007 Maxim Integrated Products
SPRINGER
is a registered trademark of Maxim Integrated Products, Inc.

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